CY74FCT273T Datasheet | Texas Instruments

description The ’FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop’s Q output. All outputs are forced low by a low logic level on the MR input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Q3 D0 GND Q0 CP MR Q4 D4 Q7 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A - MARCH 1995 - REVISED OCTOBER 2001 CY54FCT273T . . . D PACKAGE CY74FCT273T . . . Q OR SO PACKAGE (TOP VIEW) Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP CY54FCT273T . . . L PACKAGE (TOP VIEW) 3 2 1 20 19 D1 4 18 D7 Q1 5 17 D6 Q2 6 16 Q6 D2 7 15 Q5 D3 8 14 D5 9 10 11 12 13 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2001, Texas Instruments Incorporated 1 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A - MARCH 1995 - REVISED OCTOBER 2001 ORDERING...