DRA80M Description
Product Folder Order Now Technical Documents Tools & Software Support & munity ADVANCE INFORMATION DRA80xM Jacinto™ Infotainment Applications Processor Silicon Revision 2.0 DRA80M SPRSP54 APRIL 2020 1 Device Overview 1.1.
DRA80M Key Features
- Dual- or quad-core Arm® Cortex®-A53
- Up to two dual-core or two single-core Arm®
- Each A53 core has 32KB L1 ICache and 32KB L1 DCache
- Dual-core Arm® Cortex®-R5F at up to 400 MHz
- Supports lockstep mode
- 16KB ICache, 16KB DCache, and 64KB RAM per R5F core
- Three industrial subsystem with Ethernet support
- Up to two 10/100/1000 Ethernet ports per subsystem
- Supports two 10/100/1000 SGMII ports (1)
- patibility with 10/100Mb