DRA80M Datasheet PDF

APPLICATIONS

Processor Silicon Revision 2.0 DRA80M SPRSP54 – APRIL 2020 1 Device Overview 1.1

FEATURES

1Processor cores:
● Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32KB L1 DCache
● Dual-core Arm® Cortex®-R5F at up to 400 MHz – Supports lockstep mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F core Ethernet subsystem:
● Three industrial subsystem with Ethernet support: – Up to two 10/100/1000 Ethernet ports per subsystem – Supports two 10/100/1000 SGMII ports (1) – Compatibility with 10/100Mb Memory subsystem:
● Up to 2MB of on-chip L3 RAM with SECDED
● Multi-core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED – Shared coherent Level 2 or Level 3 memorymapped SRAM – Shared coherent Level 3 Cache – 256-bit processor port bus and 40-bit physical address bus – Coherent unified b...