DRA829V Overview
Product Folder Order Now Technical Documents Tools & Software Support & munity ADVANCE INFORMATION DRA829V Jacinto™ Automotive Processors Silicon Revision 1.0 DRA829V SPRSP50 DECEMBER 2019 1 Device Overview 1.1.
DRA829V Key Features
- Dual 64-bit Arm® Cortex®-A72 microprocessor
- 1MB shared L2 cache per dual-core Arm®
- 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core
- Four Arm® Cortex®-R5F MCUs at up to 1.0 GHz, 8K DMIPS
- 64K L2 RAM per core memory
- 2MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- External Memory Interface (EMIF) module with ECC