DRA829V
Overview
1.1 Features
1Processor cores:
- Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
- 1MB shared L2 cache per dual-core Arm®
Cortex®-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core
- Four Arm® Cortex®-R5F MCUs at up to 1.0 GHz, 8K DMIPS
- 64K L2 RAM per core memory
Memory subsystem:
- 2MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- External Memory Interface (EMIF) module with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 3733 MT/s
- 32-bit data bus with inline ECC up to 14.9GB/s
- General-Purpose Memory Controller (GPMC)
- 512KB on-chip SRAM in MAIN domain, protected by ECC
Safety: targeted to meet ASIL-C for MCU island and ASIL-B for main processor
- Integrated MCU island subsystem of Dual Arm® Cortex®-R5F cores with floating point coprocessor and optional lockstep operation, targeted to meet ASIL-C safety requirements/certification
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