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ADVANCE INFORMATION
DRA829V Jacinto™ Automotive Processors Silicon Revision 1.0
SPRSP50
- DECEMBER 2019
1 Device Overview
1.1 Features
1Processor cores:
- Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
- 1MB shared L2 cache per dual-core Arm®
Cortex®-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core
- Four Arm® Cortex®-R5F MCUs at up to 1.0 GHz, 8K DMIPS
- 64K L2 RAM per core memory
Memory subsystem:
- 2MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- External...