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DRA829V Datasheet Preview

DRA829V Datasheet

Automotive Processor

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DRA829V Jacinto™ Automotive Processors
Silicon Revision 1.0
DRA829V
SPRSP50 – DECEMBER 2019
1 Device Overview
1.1 Features
1Processor cores:
• Dual 64-bit Arm® Cortex®-A72 microprocessor
subsystem at up to 2.0 GHz, 24K DMIPS
– 1MB shared L2 cache per dual-core Arm®
Cortex®-A72 cluster
– 32KB L1 DCache and 48KB L1 ICache per
Cortex®-A72 Core
• Four Arm® Cortex®-R5F MCUs at up to 1.0 GHz,
8K DMIPS
– 64K L2 RAM per core memory
Memory subsystem:
• 2MB of on-chip L3 RAM with ECC and coherency
– ECC error protection
– Shared coherent cache
– Supports internal DMA engine
• External Memory Interface (EMIF) module with
ECC
– Supports LPDDR4 memory types
– Supports speeds up to 3733 MT/s
– 32-bit data bus with inline ECC up to 14.9GB/s
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected
by ECC
Safety: targeted to meet ASIL-C for MCU island
and ASIL-B for main processor
• Integrated MCU island subsystem of Dual Arm®
Cortex®-R5F cores with floating point coprocessor
and optional lockstep operation, targeted to meet
ASIL-C safety requirements/certification
– 512B Scratchpad RAM memory
– Up to 1MB on-chip RAM with ECC dedicated for
R5F
– Integrated Arm® Cortex®-R5F MCU island
isolated on separate voltage and clock domains
– Dedicated memory and interfaces capable of
being isolated from the larger SoC
• The DRA829 main processor is targeted to meet
ASIL-B safety requirements/certification
– Widespread ECC protection of on-chip memory
and interconnect
– Built-in self-test (BIST) and fault-injection for
CPU and on-chip RAM
– Error Signaling Module (ESM) with error pin
– Runtime safety diagnostics, voltage,
temperature, and clock monitoring, windowed
watchdog timers, CRC engine for memory
1
integrity checks
– Safety documentation available for applications
required to meet ISO 26262 requirements
Capture subsystem:
• Two CSI2.0 4L RX plus one CSI2.0 4L TX
Display subsystem:
• One eDP/DP interface with Multi-Display Support
(MST)
– HDCP1.4/HDCP2.2 high-bandwidth digital
content protection
• One DSI TX (up to 2.5K)
• Up to two DPI
Device security:
• Secure boot with secure runtime support
• Customer programmable root key, up to RSA-4K
or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC,
AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
• Integrated ethernet switch supporting
(total of 8 external ports)
– Up to eight 2.5Gb SGMII
– Up to eight RMII (10/100) or RGMII
(10/100/1000)
– Up to two QSGMII
• Up to four PCI-Express® (PCIe) Gen3 controllers
– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
(8.0GT/s) operation with auto-negotiation
– Up to two lanes per controller
• Two USB 3.0 dual-role device (DRD) subsystem
– Two enhanced SuperSpeed Gen1 ports
– Each port supports Type-C switching
– Each port independently configurable as USB
host, USB peripheral, or USB DRD
Automotive interfaces:
• Sixteen Modular Controller Area Network (MCAN)
modules with full CAN-FD support
Audio interfaces:
• Twelve Multichannel Audio Serial Port (MCASP)
modules
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.




etcTI

DRA829V Datasheet Preview

DRA829V Datasheet

Automotive Processor

No Preview Available !

DRA829V
SPRSP50 – DECEMBER 2019
www.ti.com
Flash memory interfaces:
• Embedded MultiMediaCard interface ( eMMC™
5.1)
• Universal Flash Storage (UFS 2.1) interface with
two lanes
• Two Secure Digital® 3.0/Secure Digital Input
Output 3.0 interfaces (SD3.0/SDIO3.0)
• Two simultaneous flash interfaces configured as
– One OSPI and one QSPI flash interfaces
1.2 Applications
Digital cockpit
Head unit
Reconfigurable digital cluster
– or HyperBus™ and QSPI flash interface
System-on-Chip (SoC) architecture:
• 16-nm FinFET technology
• 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA
(ALF), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management
ICs (PMIC):
• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases
Automotive gateway
Body control module
1.3 Description
Jacinto™ 7 DRA829V automotive processors, based on the Arm®v8 64-bit architecture, provide advanced
system integration to enable lower system costs of automotive applications such as Gateway, Vehicle
Compute, and Body Domain Controller. The integrated diagnostics and functional safety features are
targeted to ASIL-B/C certification/requirements. The integrated microcontroller (MCU) island eliminates the
need for an external system MCU. The device features a Gigabit Ethernet switch and a PCIe® hub which
enables networking use cases that require heavy data bandwidth. Up to four Arm® Cortex®-R5F
subsystems manage low level, timing critical processing tasks leaving the Arm® Cortex®-A72’s
unencumbered for applications. A dual-core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS
applications with minimal need for a software hypervisor.
PART NUMBER
Device Information(1)
PACKAGE
BODY SIZE
XDRA829VXXGALF
FCBGA (827)
24.0 mm × 24.0 mm
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.
2
Device Overview
Submit Documentation Feedback
Product Folder Links: DRA829V
Copyright © 2019, Texas Instruments Incorporated



Part Number DRA829V
Description Automotive Processor
Maker etcTI
Total Page 3 Pages
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