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SNLS013F
- JUNE 1998
- REVISED JUNE 2016
DS90LV028A 3-V LVDS Dual CMOS Differential Line Receiver
1 Features
- 1 >400-Mbps (200 MHz) Switching Rates
- 50-ps Differential Skew (Typical)
- 0.1-ns Channel-to-Channel Skew (Typical)
- 2.5-ns Maximum Propagation Delay
- 3.3-V Power Supply Design
- Flow-Through Pinout
- Power Down High Impedance on LVDS Inputs
- Low Power Design (18 mW at 3.3-V static)
- Interoperable with Existing 5-V LVDS Networks
- Accepts Small Swing (350 mV Typical) Differential
Signal Levels
- Supports Open, Short and Terminated Input Fail-
Safe
- Conforms to ANSI/TIA/EIA-644...
