LMK5B33414 Datasheet | Texas Instruments

Features - Ultra-low jitter BAW VCO based Ethernet clocks - 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz - 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz - 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) - Programmable DPLL loop bandwidth from 1 m Hz to 4 k Hz - < 1-ppt DCO frequency adjustment step size - 4 differential or single-ended DPLL inputs - 1-Hz (1-PPS) to 800-MHz input frequency - Digital holdover and hitless switching - 14 differential outputs with programmable HSDS/ LVPECL, LVDS and HSCL output formats - Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 12 differential outputs - 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and mon mode - PCIe Gen 1 to 6 pliant - I2C or 3-wire/4-wire SPI interface 2 Applications - Wired networking - Inter/Intra DC interconnect - Timing card - Line card - Fixed card (pizza box) - Sync E (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE 1588 PTP secondary clock - Jitter cleaning, wander attenuation and reference clock generation for 56G/112G PAM-4 Ser Des - 100G-800G data center switches, core routers, edge routers, WLAN - Data center and enterprise puting - Smart Network Interface Card (NIC) - Optical Transport Networks (OTN G.709) - Broadband fixed line access - Industrial - Test and measurement - Medical imaging 3 Description The LMK5B33414 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D). The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input. APLL3 features ultra high performance PLL with TI's proprietary...