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LP2995 Datasheet Preview

LP2995 Datasheet

DDR Termination Regulator

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LP2995
www.ti.com
SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013
LP2995 DDR Termination Regulator
Check for Samples: LP2995
FEATURES
1
2 Low Output Voltage Offset
• Works with +5v, +3.3v and 2.5v Rails
• Source and Sink Current
• Low External Component Count
• No External Resistors Required
• Linear Topology
• Available in SOIC-8, SO PowerPAD-8 or
WQFN-16 Packages
• Low Cost and Easy to Use
APPLICATIONS
• DDR Termination Voltage
• SSTL-2
• SSTL-3
DESCRIPTION
The LP2995 linear regulator is designed to meet the
JEDEC SSTL-2 and SSTL-3 specifications for
termination of DDR-SDRAM. The device contains a
high-speed operational amplifier to provide excellent
response to load transients. The output stage
prevents shoot through while delivering 1.5A
continuous current and transient peaks up to 3A in
the application as required for DDR-SDRAM
termination. The LP2995 also incorporates a VSENSE
pin to provide superior load regulation and a VREF
output as a reference for the chipset and DDR
DIMMS.
WHITE SPACE
WHITE SPACE
WHITE SPACE
WHITE SPACE
Typical Application Circuit
VDDQ = 2.5V
VDD = 2.5V
+
50PF
LP2995
VDDQ
AVIN
VREF
VSENSE
PVIN
VTT
GND
VREF = 1.25V
+
0.1PF
+
220PF
VTT = 1.25V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated




etcTI

LP2995 Datasheet Preview

LP2995 Datasheet

DDR Termination Regulator

No Preview Available !

LP2995
SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013
Connection Diagram
NC 1
GND 2
VSENSE 3
VREF 4
8 VTT
7 PVIN
6 AVIN
5 VDDQ
www.ti.com
N/C
GND
N/C
N/C
16 15 14 13
1
12
2
11
GND
3
10
4
9
5678
PVIN
PVIN
AVIN
N/C
Figure 1. SOIC-8 (D0008A) Package
Top View
Figure 2. NHP- 16 Package
Top View
SOIC-8 Pin or SO
PowerPAD-8 Pin
1
2
3
4
5
6
7
8
NC 1
GND 2
VSENSE 3
VREF 4
GND
8 VTT
7 PVIN
6 AVIN
5 VDDQ
Figure 3. SO PowerPAD-8 (DDA0008A) Package
Top View
WQFN Pin
1,3,4,6,9, 13,16
2
5
7
8
10
11, 12
14, 15
EP
PIN DESCRIPTIONS
Name
Function
NC
GND
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
EP
No internal connection. Can be used for vias.
Ground.
Feedback pin for regulating VTT.
Buffered internal reference voltage of VDDQ/2.
Input for internal reference equal to VDDQ/2.
Analog input pin.
Power input pin.
Output voltage for connection to termination resistors.
Exposed pad thermal connection. Connect to Ground.
2
Submit Documentation Feedback
Product Folder Links: LP2995
Copyright © 2002–2013, Texas Instruments Incorporated


Part Number LP2995
Description DDR Termination Regulator
Maker etcTI
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