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PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
Dual Bidirectional I2C Bus and SMBus Repeater
1 Features
•1 Two-Channel Bidirectional Buffers
• I2C Bus and SMBus Compatible
• Active-High Repeater-Enable Input
• Open-Drain I2C I/O
• 5.5-V Tolerant I2C I/O and Enable Input Support
Mixed-Mode Signal Operation
• Lockup-Free Operation
• Accommodates Standard Mode and Fast Mode
I2C Devices and Multiple Masters
• Powered-Off High-Impedance I2C Pins
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Description
This dual bidirectional I2C buffer is operational at 2.3-
V to 3.6-V VCC.
The PCA9515A is a BiCMOS integrated circuit
intended for I2C bus and SMBus systems
applications. The device contains two identical
bidirectional open-drain buffer circuits that enable I2C
and similar bus systems to be extended without
degradation of system performance.
The PCA9515A buffers both the serial data (SDA)
and serial clock (SCL) signals on the I2C bus, while
retaining all the operating modes and features of the
I2C system. This enables two buses of 400-pF bus
capacitance to be connected in an I2C application.
The I2C bus capacitance limit of 400 pF restricts the
number of devices and bus length. Using the
PCA9515A enables the system designer to isolate
two halves of a bus, accommodating more I2C
devices or longer trace lengths.
The PCA9515A has an active-high enable (EN) input
with an internal pullup, which allows the user to select
when the repeater is active. This can be used to
isolate a badly behaved slave on power-up reset. It
never should change state during an I2C operation,
because disabling during a bus operation hangs the
bus, and enabling part way through a bus cycle could
confuse the I2C parts being enabled. The EN input
should change state only when the global bus and
the repeater port are in an idle state, to prevent
system failures.
The PCA9515A also can be used to run two buses:
one at 5-V interface levels and the other at 3.3-V
interface levels, or one at 400-kHz operating
frequency and the other at 100-kHz operating
frequency. If the two buses are operating at different
frequencies, the 100-kHz bus must be isolated when
the 400-kHz operation of the other bus is required. If
the master is running at 400 kHz, the maximum
system operating frequency may be less than
400 kHz, because of the delays that are added by the
repeater.
The PCA9515A does not support clock stretching
across the repeater.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
PCA9515A
SOIC (8)
SON (8)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
NC
SCL0
SDA0
GND
1
2
3
4
8 VCC
7 SCL1
6 SDA1
5 EN
DRG PACKAGE
(TOP VIEW)
NC
SCL0
SDA0
GND
1
2
3
4
8 VCC
7 SCL1
6 SDA1
5 EN
NC – No internal connection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
