SM320C6201B Datasheet | Texas Instruments

Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B) D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM -- Glueless Interface to Asynchronous Memories: SRAM and EPROM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999 GLE and GLP PACKAGES (BOTTOM VIEW) AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 D 16-Bit Host-Port Interface (HPI) -- Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (Mc BSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching patible -- Up to 256 Channels Each -- AC97-patible -- Serial Peripheral Interface (SPI) patible (Motorola™) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan patible D 429-Pin BGA Package (GLE Suffix) (’6201) D 429-Pin BGA Package (GLP Suffix) (’6201B) D CMOS Technology -- 0.25-μm/5-Level Metal Process (’6201) -- 0.18-μm/5-Level Metal Process (’6201B) D 3.3-V I/Os, 2.5-V Internal (’6201) D 3.3-V I/Os, 1.8-V Internal (’6201B) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Veloci TI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan...