SM320C6201B
Description
CLOCK/PLL CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 CLKMODE0 C17 Clock mode select I - Selects whether the output clock frequency = input clock freq x4 or x1 PLLFREQ3 C13 PLL frequency range (3, 2, and 1) PLLFREQ2 G11 I - Selects one of three frequency ranges bounding the CLKOUT1 signal. PLLFREQ1 F11 - CLKOUT1 frequency determines the 3-bit value for the PLLFREQ pins.
Key Features
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201)
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
