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SM320C6201B Datasheet Preview

SM320C6201B Datasheet

Digital Signal Processor

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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
D Highest Performance Fixed-Point Digital
Signal Processor (DSP) SM320C6201
-- 6.67-ns Instruction Cycle Time
-- 150-MHz Clock Rate
-- Eight 32-Bit Instructions/Cycle
-- 1200 MIPS
D Highest Performance Fixed-Point Digital
Signal Processor (DSP) SMJ320C6201B
-- 6.67-ns Instruction Cycle Time
-- 150-MHz Clock Rate
-- Eight 32-Bit Instructions/Cycle
-- 1200 MIPS
D VelociTIAdvanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core
-- Eight Independent Functional Units:
-- Six ALUs (32-/40-Bit)
-- Two 16-Bit Multipliers (32-Bit Results)
-- Load-Store Architecture With 32 32-Bit
General-Purpose Registers
-- Instruction Packing Reduces Code Size
-- All Instructions Conditional
D Instruction Set Features
-- Byte-Addressable (8-, 16-, 32-Bit Data)
-- 32-Bit Address Range
-- 8-Bit Overflow Protection
-- Saturation
-- Bit-Field Extract, Set, Clear
-- Bit-Counting
-- Normalization
D 1M-Bit On-Chip SRAM
-- 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
-- 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as a Single Block
(’6201)
-- 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency (’6201B)
D 32-Bit External Memory Interface (EMIF)
-- Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
-- Glueless Interface to Asynchronous
Memories: SRAM and EPROM
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
GLE and GLP PACKAGES
(BOTTOM VIEW)
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21
2 4 6 8 10 12 14 16 18 20
D 16-Bit Host-Port Interface (HPI)
-- Access to Entire Memory Map
D Two Multichannel Buffered Serial Ports
(McBSPs)
-- Direct Interface to T1/E1, MVIP, SCSA
Framers
-- ST-Bus-Switching Compatible
-- Up to 256 Channels Each
-- AC97-Compatible
-- Serial Peripheral Interface (SPI)
Compatible (Motorola)
D Two 32-Bit General-Purpose Timers
D Flexible Phase-Locked Loop (PLL) Clock
Generator
D IEEE-1149.1 (JTAG) Boundary-Scan
Compatible
D 429-Pin BGA Package (GLE Suffix) (’6201)
D 429-Pin BGA Package (GLP Suffix) (’6201B)
D CMOS Technology
-- 0.25-μm/5-Level Metal Process (’6201)
-- 0.18-μm/5-Level Metal Process (’6201B)
D 3.3-V I/Os, 2.5-V Internal (’6201)
D 3.3-V I/Os, 1.8-V Internal (’6201B)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
Copyright © 1998, Texas Instruments Incorporated
1




etcTI

SM320C6201B Datasheet Preview

SM320C6201B Datasheet

Digital Signal Processor

No Preview Available !

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
Signal Descriptions
SIGNAL
NAME
NO.
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O Clock output at full device speed
CLKOUT2
V9
O Clock output at half of device speed
CLKMODE1
B17
CLKMODE0
C17
Clock mode select
I
Selects whether the output clock frequency = input clock freq x4 or x1
PLLFREQ3
C13
PLL frequency range (3, 2, and 1)
PLLFREQ2
G11
I
Selects one of three frequency ranges bounding the CLKOUT1 signal.
PLLFREQ1
F11
CLKOUT1 frequency determines the 3-bit value for the PLLFREQ pins.
PLLV
PLLG
D12
A§ PLL analog VCC connection for the low-pass filter
G10
A§ PLL analog GND connection for the low-pass filter
PLLF
C12
A§ PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
K19
I
JTAG test port mode select (features an internal pull-up)
TDO
R12
O/Z JTAG test port data out
TDI
R13
I
JTAG test port data in (features an internal pull-up)
TCK
M20
I
JTAG test port clock
TRST
EMU1
EMU0
N18
I
JTAG test port reset (features an internal pull-down)
R20 I/O/Z Emulation pin 1, pull-up with a dedicated 20-kresistor
T18
I/O/Z Emulation pin 0, pull-up with a dedicated 20-kresistor
CONTROL
RESET
J20
I
Device reset
NMI
K21
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
R16
EXT_INT6
EXT_INT5
P20
External interrupts
R15
I
Edge-driven (rising edge)
EXT_INT4
R18
IACK
R11
O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
INUM2
INUM1
INUM0
T19
T20
Active interrupt identification number
O Valid during IACK for all active interrupts (not just external)
T14
Encoding order follows the interrupt service fetch packet ordering
T16
LENDIAN
G20
I
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
PD
D19
O Power-down mode 3 (active if high)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
§ A = Analog Signal (PLL Filter)
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443



Part Number SM320C6201B
Description Digital Signal Processor
Maker etcTI
Total Page 3 Pages
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SM320C6201B Datasheet PDF





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