SM320C6201B
Description
lock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 CLKMODE0 C17 Clock mode select I • Selects whether the output clock frequency = input clock freq x4 or x1 PLLFREQ3 C13 PLL frequency range (3, 2, and 1) PLLFREQ2 G11 I • Selects one of three frequency ranges bounding the CLKOUT1 signal.
Key Features
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B)
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Access to Entire Memory Map
- POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
