SM320C6201-EP
Overview
- 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
- 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI) -- Access to Entire Memory Map
- Two Multichannel Buffered Serial Ports (McBSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching Compatible -- Up to 256 Channels Each -- AC97-Compatible -- Serial Peripheral Interface (SPI) Compatible (Motorola™)
- Two 32-Bit General-Purpose Timers
- Flexible Phase-Locked Loop (PLL) Clock Generator
- IEEE-1149.1 (JTAG‡) Boundary-Scan Compatible
- 352-Pin BGA Package (GJC Suffix)
