SM320C6201B Description
-- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Results) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set.
SM320C6201B Key Features
- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B)
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Access to Entire Memory Map
- 0.25-μm/5-Level Metal Process (’6201) -- 0.18-μm/5-Level Metal Process (’6201B)