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SM320C6701-EP Datasheet Preview

SM320C6701-EP Datasheet

Digital Signal Processor

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SM320C6701ĆEP, SM320C6701MECHĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance up to
−40°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Highest Performance Floating-Point Digital
Signal Processor (DSP) 320C6701
− 8.3-, 6-ns Instruction Cycle Time
− 120-, 167-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 1 GFLOPS
− 320C6201 Fixed-Point DSP
Pin-Compatible
D VelociTIAdvanced Very Long Instruction
Word (VLIW) C67x CPU Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Hardware Support for IEEE
Single-Precision Instructions
− Hardware Support for IEEE
Double-Precision Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
SGUS042A − MAY 1998 − REVISED APRIL 2004
D 1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data
(64K Bytes)
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D 16-Bit Host-Port Interface (HPI)
− Access to Entire Memory Map
D Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
D Two 32-Bit General-Purpose Timers
D Flexible Phase-Locked-Loop (PLL) Clock
Generator
D IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
D 352-Pin Ball Grid Array (BGA) Package
(GJC Suffix)
D 352-Pin Ball Grid Array (BGA) Mechanical
Shock-Tolerant Package (Mech~Shock)
Option (GJC Suffix)
D 0.18-µm/5-Level Metal Process
− CMOS Technology
D 3.3-V I/Os, 1.8-V Internal (120-MHz)
D 3.3-V I/Os, 1.9-V Internal (167-MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1




etcTI

SM320C6701-EP Datasheet Preview

SM320C6701-EP Datasheet

Digital Signal Processor

No Preview Available !

SM320C6701ĆEP, SM320C6701MECHĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A − MAY 1998 − REVISED APRIL 2004
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 4
CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
recommended operating conditions . . . . . . . . . . . . . . . . . . . 26
electrical characteristics over recommended ranges of
supply voltage and operating case temperature . . . . 26
parameter measurement information . . . . . . . . . . . . . . . 27
signal-transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 31
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 33
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 37
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 44
host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 45
multichannel buffered serial port timing . . . . . . . . . . . . . 48
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 59
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
description
GJC (352-PIN BGA) PACKAGE
( BOTTOM VIEW )
The 320C67x DSPs are the floating-point DSP
26
1
family in the TMS320C6000DSP platform. The
A
SM320C6701-EP and SM320C6701MECH-EP
B
C
(C6701) devices are based on the high-
D
E
performance, advanced VelociTI very-long-
F
instruction-word (VLIW) architecture developed
G
H
by Texas Instruments (TI), making this DSP an
J
excellent choice for multichannel and
K
L
multifunction applications. With performance of
M
N
up to 1 giga floating-point operations per second
P
(GFLOPS) at a clock rate of 167 MHz, the C6701
R
T
offers cost-effective solutions to high-
U
V
performance DSP programming challenges. The
W
C6701 DSP possesses the operational flexibility
Y
AA
of high-speed controllers and the numerical
AB
AC
capability of array processors. This processor has
AD
32 general-purpose registers of 32-bit word length
AE
AF
and eight highly independent functional units. The
eight functional units provide four floating-/fixed-
point ALUs, two fixed-point ALUs, and two
floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total
of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic,
on-chip memory, and additional on-chip peripherals.
The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443



Part Number SM320C6701-EP
Description Digital Signal Processor
Maker etcTI
Total Page 3 Pages
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