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SN54AHCT139 Datasheet Preview

SN54AHCT139 Datasheet

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

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SN54AHCT139, SN74AHCT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
D Inputs Are TTL-Voltage Compatible
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHCT139 devices are dual 2-line to 4-line
decoders/demultiplexers designed for 4.5-V to
5.5-V VCC operation. These devices are
designed to be used in high-performance
memory-decoding or data-routing applications
requiring very short propagation delay times. In
high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When used with high-speed
memories utilizing a fast enable circuit, the delay
times of these decoders and the enable time of the
memory usually are less than the typical access
time of the memory. This means that the effective
system delay introduced by the decoders is
negligible.
SCLS267M – DECEMBER 1995 – REVISED MARCH 2003
SN54AHCT139 . . . J OR W PACKAGE
SN74AHCT139 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
1G 1
1A 2
1B 3
1Y0 4
1Y1 5
1Y2 6
1Y3 7
GND 8
16 VCC
15 2G
14 2A
13 2B
12 2Y0
11 2Y1
10 2Y2
9 2Y3
SN54AHCT139 . . . FK PACKAGE
(TOP VIEW)
1B
3 2 1 20 19
4
18
2A
1Y0 5
17 2B
NC 6
16 NC
1Y1 7
15 2Y0
1Y2 8
14 2Y1
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74AHCT139N
SN74AHCT139N
SOIC – D
Tube
Tape and reel
SN74AHCT139D
SN74AHCT139DR
AHCT139
–40°C to 85°C
SOP – NS
SSOP – DB
Tape and reel
Tape and reel
SN74AHCT139NSR
SN74AHCT139DBR
AHCT139
HB139
TSSOP – PW
Tube
Tape and reel
SN74AHCT139PW
SN74AHCT139PWR
HB139
TVSOP – DGV
Tape and reel SN74AHCT139DGVR HB139
CDIP – J
Tube
SNJ54AHCT139J
SNJ54AHCT139J
–55°C to 125°C CFP – W
Tube
SNJ54AHCT139W
SNJ54AHCT139W
LCCC – FK
Tube
SNJ54AHCT13FK
SNJ54AHCT139FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




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SN54AHCT139 Datasheet Preview

SN54AHCT139 Datasheet

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

No Preview Available !

SN54AHCT139, SN74AHCT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS267M DECEMBER 1995 REVISED MARCH 2003
description/ordering information (continued)
The active-low enable (G) input can be used as a data line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit.
FUNCTION TABLE
(each decoder/demultiplexer)
INPUTS
SELECT
G
B
A
OUTPUTS
Y0 Y1 Y2 Y3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
logic diagram (positive logic)
1
1G
Select
Inputs
2
1A
3
1B
15
2G
Select
Inputs
14
2A
13
2B
4
1Y0
5
1Y1
6
1Y2
7
1Y3
12
2Y0
11
2Y1
10
2Y2
Data
Outputs
9
2Y3
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN54AHCT139
Description DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
Maker etcTI
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