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SN54HC195 - 4-BIT PARALLEL-ACCESS SHIFT REGISTERS

General Description

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear.

The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Key Features

  • 1.
  • Synchronous Parallel Load.
  • Positive-Edge-Triggered Clocking.
  • J and K Inputs to First Stage.
  • Complementary Outputs From Last Stage.
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers.
  • Dependable Texas lnstruments Quality and Reliability.

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Other Datasheets by Texas Instruments

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SN54HC195J 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com FEATURES 1 • Synchronous Parallel Load • Positive-Edge-Triggered Clocking • J and K Inputs to First Stage • Complementary Outputs From Last Stage • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers • Dependable Texas lnstruments Quality and Reliability DESCRIPTION/ORDERING INFORMATION These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD). Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input.