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SN54HC195J - 4-BIT PARALLEL-ACCESS SHIFT REGISTERS

Download the SN54HC195J datasheet PDF. This datasheet also covers the SN54HC195 variant, as both devices belong to the same 4-bit parallel-access shift registers family and are provided as variant models within a single manufacturer datasheet.

General Description

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear.

The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Key Features

  • 1.
  • Synchronous Parallel Load.
  • Positive-Edge-Triggered Clocking.
  • J and K Inputs to First Stage.
  • Complementary Outputs From Last Stage.
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers.
  • Dependable Texas lnstruments Quality and Reliability.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN54HC195-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
SN54HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SN54HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS
SN54HC10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SN54HC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com FEATURES 1 • Synchronous Parallel Load • Positive-Edge-Triggered Clocking • J and K Inputs to First Stage • Complementary Outputs From Last Stage • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers • Dependable Texas lnstruments Quality and Reliability DESCRIPTION/ORDERING INFORMATION These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD). Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input.