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SN54HC20J - Dual 4-Input NAND Gates

Download the SN54HC20J datasheet PDF. This datasheet also covers the SN54HC20 variant, as both devices belong to the same dual 4-input nand gates family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (SN54HC20-etcTI.pdf) that lists specifications for multiple related part numbers.

General Description

This device contains two independent 4-input NAND gates.

Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic.

Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC20D SOIC (14) 8.70 mm × 3.90 mm SN74HC20N PDIP (14) 19.30 mm × 6.40 mm SN74HC20NS SO (14) 10.20 mm × 5.30 mm SN74HC20PW TSSOP (14) 5.00 mm × 4.40 mm SN54HC20J CDIP (14) 21.30 mm × 7.60 mm SN54HC20W CFP (14) 9.20 mm × 6.29 mm SN54HC20FK LCCC (20) 8.90 mm × 8.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

Overview

www.ti.com SCLS086G – DECEMBERSS1NN9877244–HHRCCEV22I00S,,ESSDNNAP55R44IHHL CC20222001 SCLS086G – DECEMBER 1982 – REVISED APRIL 2021 SNx4HC20 Dual 4-Input NAND Gates.

Key Features

  • Buffered inputs.
  • Wide operating voltage range: 2 V to 6 V.
  • Wide operating temperature range:.
  • 40°C to +85°C.
  • Supports fanout up to 10 LSTTL loads.
  • Significant power reduction compared to LSTTL logic ICs 2.