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SN54LS273 - OCTAL D-TYPE FLIP-FLOP

Download the SN54LS273 datasheet PDF. This datasheet also covers the SN54273 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN54273-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
SN54LS273 OCTAL D FLIP-FLOP Motorola
SN54LS279 QUAD SET-RESET LATCH Motorola
SN54LS20 DUAL 4-INPUT NAND GATE Motorola Inc
SN54LS21 DUAL 4-INPUT AND GATE Motorola Inc
SN54LS22 DUAL 4-INPUT NAND GATE Motorola Inc

Other Datasheets by Texas Instruments

Part Number Description
SN54LS27 Triple 3-Input Positive-NOR Gates
SN54LS279A QUADRUPLE S-R LATCHES
SN54LS20 Dual 4-Input Positive-NAND Gate
SN54LS21 DUAL 4-INPUT POSITIVE-AND GATE
SN54LS221 DUAL MONOSTABLE MULTIVIBRATORS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
• Contains Eight Flip-Flops With Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators description These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output.