SN65LVDS108 Overview
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs. The line receivers and line drivers implement the of low-voltage differential signaling (LVDS).
SN65LVDS108 Key Features
- One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater
- Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load
- Electrically patible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Terminat
- Propagation Delay Times < 4.7 ns
- Output Skew Less Than 300 ps and
- Total Power Dissipation at 200 MHz Typically Less Than 330 mW With 8 Channels Enabled
- Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V