SN65LVDS17 stage/buffers equivalent, 2.5-v/3.3-v oscillator gain stage/buffers.
* Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
* Clock Rates to 2 GHz
– 140-ps Output Transition Times
– 0.11 ps Ty.
* PECL-to-LVDS Translation
* Clock Signal Amplification
DESCRIPTION
These four devices are high-frequency oscil.
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