SN65LVDS310 Overview
The SN65LVDS310 receiver deserializes FlatLink 3G-pliant serial input data to 27 parallel data outputs. The SN65LVDS310 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel.
SN65LVDS310 Key Features
- Serial Interface Technology
- patible With FlatLink™ 3G Transmitters
- Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Data Line
- SubLVDS Differential Voltage Levels
- Up to 405-Mbps Data Throughput
- Three Operating Modes to Conserve Power
- Active mode QVGA: 17 mW
- Typical Shutdown: 0.7 µW
- Typical Standby Mode: 67 µW Typical
- ESD Rating > 4 kV (HBM)