Datasheet Summary
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
D High-Drive Outputs (- 32-mA IOH, 64-mA IOL) D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (N) and Ceramic (J) DIPs
SN54ABT373, SN74ABT373 OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS155D
- JANUARY 1991
- REVISED MAY 1997
SN54ABT373 . . . J OR W PACKAGE SN74ABT373 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
OE 1 1Q 2 1D...