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SN74AHC125-EP - QUADRUPLE BUS BUFFER GATE

General Description

The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs.

Each output is disabled when the associated output-enable (OE) input is high.

When OE is low, the respective gate passes the data from the A input to its Y output.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D Controlled Baseline – One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of –55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D EPIC (Enhanced-Performance Implanted CMOS) Process D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 150 V Using Machine Model (C = 200 pF, R = 0) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.