DQualified for Automotive Applications
DESD Protection Exceeds 1000 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
Using Machine Model (C = 200 pF, R = 0)
DEPIC (Enhanced-Performance Implanted
DOperating Range 2-V to 5.5-V VCC
DLatch-Up Performance Exceeds 250 mA Per
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS525A − AUGUST 2003 − REVISED APRIL 2008
D OR PW PACKAGE
The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each
output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate
passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
−40°C to 125°C
SOIC − D
TSSOP − PW
Tape and reel
Tape and reel
† For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
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