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SN74AHC74Q-Q1 Datasheet Preview

SN74AHC74Q-Q1 Datasheet

Dual Positive-Edge-Triggered D-Type Flip-Flop

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SN74AHC74QĆQ1
DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP
WITH CLEAR AND PRESET
SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008
D Qualified for Automotive Applications
D EPIC(Enhanced-Performance Implanted
CMOS) Process
D Operating Range 2-V to 5.5-V VCC
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE
(TOP VIEW)
1CLR 1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 VCC
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8 2Q
description
The SN74AHC74Q dual positive-edge-triggered device is a D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
−40°C to 125°C
TSSOP − PW
Tape and reel
Tape and reel
SN74AHC74QDRQ1 AHC74Q
SN74AHC74QPWRQ1 HA74Q
For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2008, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




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SN74AHC74Q-Q1 Datasheet Preview

SN74AHC74Q-Q1 Datasheet

Dual Positive-Edge-Triggered D-Type Flip-Flop

No Preview Available !

SN74AHC74QĆQ1
DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP
WITH CLEAR AND PRESET
SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE CLR CLK D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H† H†
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0 Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol
4
1PRE
3
1CLK
2
1D
1
1CLR
10
2PRE
11
2CLK
12
2D
13
2CLR
S
C1
1D
R
5
1Q
6
1Q
9
2Q
8
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
D
TG
TG
C
C
TG
Q
C
C
C
CLR
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74AHC74Q-Q1
Description Dual Positive-Edge-Triggered D-Type Flip-Flop
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