* GND 7 8 CLK AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level inpu
SN74ALS164A Datasheet (687.13 KB)
SN74ALS164A
687.13 KB
8-bit parallel-out serial shift register.
SN74ALS164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą SDAS159D APRIL 1982 REVISED DECEMBER 1994 AND-Gated ( Enable/Dis.
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