Texas Instruments SN74ALS165
The SN74ALS165 is characterized for operation from 0°C to 70°C.| Part No. | SN74ALS165 |
|---|---|
| Datasheet | SN74ALS165 Download |
| Manufacturer |  Texas Instruments |
| Description | Parallel-Load 8-Bit Register |
| Buy | Stock & Price |
SN54ALS165, SN74ALS165 PARALLELĆLOAD 8ĆBIT REGISTERS ą SDAS157B − JUNE 1982 − REVISED DECEMBER 1994
● Complementary Outputs
● Direct Overriding Load (Data) Inputs
● Gated Clock Inputs
● Parallel-to-Serial Data Conversion
● Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description The ′ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and QH) outputs. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ′ALS165 have a clock-inhibit function and complemented serial outputs. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high.
● Complementary Outputs
● Direct Overriding Load (Data) Inputs
● Gated Clock Inputs
● Parallel-to-Serial Data Conversion
● Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description The ′ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and QH) outputs. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ′ALS165 have a clock-inhibit function and complemented serial outputs. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high.
