SN74ALS164A Datasheet | Texas Instruments

description QC 5 QD 6 10 QE 9 CLR This 8-bit parallel-out serial shift register features GND 7 8 CLK AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit control over ining data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects. The SN74ALS164A is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS† CLR CLK A QA QB . . . QH X QA0 QB0 QH0 ↑ H QAn QGn ↑ L QAn QGn ↑ L QAn...