SN74ALS166 Datasheet | Texas Instruments

description The SN74ALS166 parallel-load 8-bit shift register is patible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design. D, DB, OR N PACKAGE (TOP VIEW) SER 1 A2 B3 C4 D5 CLK INH 6 CLK 7 GND 8 16 VCC 15 SH/LD 14 H 13 QH 12 G 11 F 10 E 9 CLR These parallel-in or serial-in, serial-out registers have a plexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A- H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is acplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on mand with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR overrides all other inputs, including CLK, and sets all flip-flops to zero. The SN74ALS166 is characterized for operation from 0°C to 70°C. L H H H H H SH/LD X X L H H X FUNCTION TABLE INPUTS PARALLEL CLK INH CLK SER A...H ↑ X a...h ↑ ↑ ↑ INTERNAL...