900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






etcTI

SN74AUC1G74 Datasheet Preview

SN74AUC1G74 Datasheet

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

No Preview Available !

www.ti.com
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.5 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
Low Power Consumption, 10-μA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RSE PACKAGE
(TOP VIEW)
YZP OR YZT PACKAGE
(BOTTOM VIEW)
CLK
1
D
2
Q
3
GND
4
8
VCC
CLK 1
D2
7
PRE
Q3
6
CLR
GND
4
5
Q
8
VCC
7 PRE
6 CLR
5Q
VCC 8
4 GND
GND 4 5 Q
Q 3 6 CLR
D 2 7 PRE
CLK
1 8 VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated




etcTI

SN74AUC1G74 Datasheet Preview

SN74AUC1G74 Datasheet

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

No Preview Available !

SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
www.ti.com
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZT (Pb-free)
Reel of 3000
Reel of 3000
SN74AUC1G74YZPR
SN74AUC1G74YZTR
_ _ _UP_
QFN – RSE
Reel of 3000 SN74AUC1G74RSER
UP
SSOP – DCT
Reel of 3000 SN74AUC1G74DCTR
U74_ _ _
VSSOP – DCU
Reel of 3000 SN74AUC1G74DCUR
U74_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP/YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
PRE
CLR
CLK
D
L
H
X
X
X
L
X
X
H
H
H
H
H
L
H
H
L
X
OUTPUTS
Q
Q
H
L
L
H
H
L
L
H
Q0
Q0
CLR 6
CLK 1
C
D2
TG
LOGIC DIAGRAM (POSITIVE LOGIC)
C
C
C
TG
C
TG
C
C
TG
3
Q
5
Q
C
C
C
PRE 7
A. Pin numbers shown are for the DCT, DCU, YZP, and YZT packages only.
2
Submit Documentation Feedback


Part Number SN74AUC1G74
Description SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Maker etcTI
PDF Download

SN74AUC1G74 Datasheet PDF






Similar Datasheet

1 SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
etcTI
2 SN74AUC1G79 Single Positive-Edge-Triggered D-type Flip-Flop
etcTI





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy