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SN74AUP1G34 - Low-Power Single Buffer Gate

Description

This single buffer gate performs the Boolean function Y = A in positive logic.

Features

  • 1 Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch.
  • Low Static-Power Consumption; ICC = 0.9 μA Max.
  • Low Dynamic-Power Consumption; Cpd = 4.1 pF Typ at 3.3 V.
  • Low Input Capacitance; Ci = 1.5 pF Typ.
  • Low Noise - Overshoot and Undershoot < 10% of VCC.
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection.
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74AUP1G34 SCES603K – AUGUST 2004 – REVISED OCTOBER 2014 SN74AUP1G34 Low-Power Single Buffer Gate 1 Features •1 Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch • Low Static-Power Consumption; ICC = 0.9 μA Max • Low Dynamic-Power Consumption; Cpd = 4.1 pF Typ at 3.3 V • Low Input Capacitance; Ci = 1.5 pF Typ • Low Noise - Overshoot and Undershoot < 10% of VCC • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V) • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation • 3.
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