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SN74AUP1G58 Datasheet Preview

SN74AUP1G58 Datasheet

LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G58
www.ti.com
SCES504J – NOVEMBER 2003 – REVISED MARCH 2010
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
Check for Samples: SN74AUP1G58
FEATURES
1
• Available in the Texas Instruments NanoStar™
Packages
• Low Static-Power Consumption
(ICC = 0.9 mA Max)
• Low Dynamic-Power Consumption
(Cpd = 4.6 pF Typ at 3.3 V)
• Low Input Capacitance (Ci = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot <10%
of VCC
• Ioff Supports Partial-Power-Down Mode
Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• tpd = 5.5 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
ln1
1
6
ln2
GND
2
5
VCC
DCK PACKAGE
(TOP VIEW)
ln1 1
6 ln2
GND 2
5
VCC
ln0 3
4
Y
DRL PACKAGE
(TOP VIEW)
ln1 1
GND 2
ln0 3
6 ln2
5 VCC
4Y
ln0
3
4
Y
DRY PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
In1 1
GND 2
In0 3
6 In2
V 5
CC
4Y
In1 1
GND 2
In0 3
6 In2
V 5
CC
4Y
See mechanical drawings for dimensions.
YFP PACKAGE
(TOP VIEW)
In1 A1 1 6 A2 In2
GND V B1 2 5 B2
CC
In0 C1 3 4 C2 Y
YZP PACKAGE
(TOP VIEW)
In1 A1 1 6 A2 In2
GND V B1 2 5 B2
CC
In0 C1 3 4 C2 Y
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,
which produces very low undershoot and overshoot characteristics.
The SN74AUP1G58 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and
better switching noise immunity at the input.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2010, Texas Instruments Incorporated




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SN74AUP1G58 Datasheet Preview

SN74AUP1G58 Datasheet

LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

No Preview Available !

SN74AUP1G58
SCES504J – NOVEMBER 2003 – REVISED MARCH 2010
www.ti.com
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE (2)
ORDERABLE PART NUMBER
–40°C to 85°C
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
uQFN – DSF
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
Reel of 3000
Reel of 3000
Reel of 5000
Reel of 5000
Reel of 3000
Reel of 3000
Reel of 4000
SN74AUP1G58YFPR
SN74AUP1G58YZPR
SN74AUP1G58DRYR
SN74AUP1G58DSFR
SN74AUP1G58DBVR
SN74AUP1G58DCKR
SN74AUP1G58DRLR
TOP-SIDE
MARKING (3)
_ _ _HJ_
_ _ _HJ_
HJ
HJ
H58_
HJ_
HJ_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
In2
In1
In0
OUTPUT
Y
L
L
L
L
L
L
H
H
L
H
L
L
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
L
H
H
H
L
In0 3
1
In1
LOGIC DIAGRAM (POSITIVE LOGIC)
4Y
6
In2
2
Submit Documentation Feedback
Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G58


Part Number SN74AUP1G58
Description LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
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