SN74AUP1T02 Overview
/ORDERING INFORMATION The SN74AUP1T02 performs the Boolean function Y = A + B or Y = A B with designation for logic-level translation applications with output referenced to supply VCC. AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.
SN74AUP1T02 Key Features
- Single-Supply Voltage Translator
- Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
- 2.5 V to 3.3 V (at VCC = 3.3 V)
- 1.8 V to 2.5 V (at VCC = 2.5 V)
- 3.3 V to 2.5 V (at VCC = 2.5 V
- Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity
- Ioff Supports Partial Power Down (VCC = 0 V)
- Very Low Static Power Consumption
- Very Low Dynamic Power Consumption: 0.9 µA