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SN74CBT3306C Datasheet Preview

SN74CBT3306C Datasheet

DUAL FET BUS SWITCH

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SN74CBT3306C
DUAL FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (ron)
Characteristics (ron = 3 Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(ICC = 3 µA Max)
D VCC Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
D OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
GND 4
8 VCC
7 2OE
6 2B
5 2A
description/ordering information
The SN74CBT3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3306C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B
ports.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tube
Tape and reel
Tube
Tape and reel
SN74CBT3306CD
SN74CBT3306CDR
SN74CBT3306CPW
SN74CBT3306CPWR
CU306C
CU306C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




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SN74CBT3306C Datasheet Preview

SN74CBT3306C Datasheet

DUAL FET BUS SWITCH

No Preview Available !

SN74CBT3306C
DUAL FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
INPUT
OE
L
H
FUNCTION TABLE
(each bus switch)
INPUT/OUTPUT
A
FUNCTION
B
A port = B port
Z
Disconnect
logic diagram (positive logic)
2
1A
1
1OE
3
SW
1B
5
2A
7
2OE
6
SW
2B
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN
EN is the internal enable signal applied to the switch.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74CBT3306C
Description DUAL FET BUS SWITCH
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