OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
D Wide Operating Voltage Range of 2 V to 6 V
D High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 11 ns
D ±6-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Independent Registers for A and B Buses
D Multiplexed Real-Time and Stored Data
D True Data Paths
SN54HC646 . . . JT OR W PACKAGE
SN74HC646 . . . DW OR NT PACKAGE
SN54HC646 . . . FK PACKAGE
4 3 2 1 28 27 26
A6 1112 13 14 15 16 17 1819
NC – No internal connection
The ’HC646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’HC646 devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port may be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be
stored in one register and /or B data may be stored in the other register.
PDIP – NT
–40°C to 85°C
SOIC – DW
Tape and reel
CDIP – JT
–55°C to 125°C CFP – W
LCCC – FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
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