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SN74HCT139 Datasheet Preview

SN74HCT139 Datasheet

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXER

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SN54HCT139, SN74HCT139
DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS
D Operating Voltage Range of 4.5 V to 5.5 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 10 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Inputs Are TTL-Voltage Compatible
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HCT139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003
SN54HCT139 . . . J OR W PACKAGE
SN74HCT139 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
1G 1
1A 2
1B 3
1Y0 4
1Y1 5
1Y2 6
1Y3 7
GND 8
16 VCC
15 2G
14 2A
13 2B
12 2Y0
11 2Y1
10 2Y2
9 2Y3
SN54HCT139 . . . FK PACKAGE
(TOP VIEW)
1B
3 2 1 20 19
4
18
2A
1Y0 5
17 2B
NC 6
16 NC
1Y1 7
15 2Y0
1Y2 8
14 2Y1
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HCT139N
SN74HCT139N
Tube of 40
SN74HCT139D
−40°C to 85°C
SOIC − D
SSOP − DB
Reel of 2500
Reel of 250
Reel of 2000
SN74HCT139DR
SN74HCT139DT
SN74HCT139DBR
HCT139
HT139
TSSOP − PW
Reel of 2000
Reel of 250
SN74HCT139PWR
SN74HCT139PWT
HT139
CDIP − J
−55°C to 125°C CFP − W
Tube of 25
Tube of 150
SNJ54HCT139J
SNJ54HCT139W
SNJ54HCT139J
SNJ54HCT139W
LCCC − FK
Tube of 55
SNJ54HCT139FK
SNJ54HCT139FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




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SN74HCT139 Datasheet Preview

SN74HCT139 Datasheet

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXER

No Preview Available !

SN54HCT139, SN74HCT139
DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS
SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The ’HCT139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low
enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers
feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
FUNCTION TABLE
INPUTS
SELECT
G
B
A
H
X
X
OUTPUTS
Y0 Y1 Y2 Y3
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
logic diagram (positive logic)
1
1G
4
1Y0
5
1Y1
2
1A
3
1B
15
2G
6
1Y2
7
1Y3
12
2Y0
11
2Y1
14
2A
13
2B
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
10
2Y2
9
2Y3
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74HCT139
Description DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXER
Maker etcTI
Total Page 3 Pages
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