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SN74LV165A-EP Datasheet Preview

SN74LV165A-EP Datasheet

Parallel-Load 8-Bit Shift Register

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FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
2-V to 5.5-V VCC Operation
Max tpd of 10.5 ns at 5 V
Supports Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SCLS694 – JANUARY 2006
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
SH/LD 1
CLK 2
E3
F4
G5
H6
QH 7
GND 8
16 VCC
15 CLK INH
14 D
13 C
12 B
11 A
10 SER
9 QH
DESCRIPTION
The SN74LV165A-EP is a parallel-load, 8-bit shift register designed for 2-V to 5.5-V VCC operation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The
SN74LV165A-EP features a clock-inhibit function and a complemented serial output, QH.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while
CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled
while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION
TA
–55°C to 125°C
PACKAGE (1)
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SN74LV165AMPWREP
LV165EP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated




etcTI

SN74LV165A-EP Datasheet Preview

SN74LV165A-EP Datasheet

Parallel-Load 8-Bit Shift Register

No Preview Available !

SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SCLS694 – JANUARY 2006
www.ti.com
SH/LD
L
H
H
H
H
FUNCTION TABLE
INPUTS
CLK
X
H
X
L
CLK INH
X
X
H
L
OPERATION
Parallel load
Q0
Q0
Shift
Shift
SH/LD 1
CLK INH 15
CLK 2
SER 10
LOGIC DIAGRAM (POSITIVE LOGIC)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
S
C1
1D
S
C1
1D
S
C1
1D
S
C1
1D
S
C1
1D
S
C1
1D
S
C1
1D
S
C1
1D
9
7
QH
QH
R
R
R
R
R
R
R
R
2


Part Number SN74LV165A-EP
Description Parallel-Load 8-Bit Shift Register
Maker etcTI
Total Page 3 Pages
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