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SN74LV20A Datasheet Dual 4-input Positive Nand Gate

Manufacturer: Texas Instruments

Overview: SN54LV20A, SN74LV20A DUAL 4ĆINPUT POSITIVEĆNAND GATE D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005 SN54LV20A . . . J OR W PACKAGE SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1A 1B NC 1C 1D 1Y GND 1 2 3 4 5 6 7 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y SN54LV20A . . .

General Description

/ordering information These dual 4-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation.

The ’LV20A devices perform the Boolean function Y = A • B • C • D or Y = A + B + C + D in positive logic.

These devices are fully specified for partial-power-down applications using Ioff.

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