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SN74LVTH373 Datasheet Preview

SN74LVTH373 Datasheet

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES

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SN54LVTH373, SN74LVTH373
3.3ĆV ABT OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCBS689H − MAY 1997 − REVISED OCTOBER 2003
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Support Unregulated Battery Operation
Down to 2.7 V
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH373 . . . J OR W PACKAGE
SN74LVTH373 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
SN54LVTH373 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These octal latches are designed specifically for
low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a
5-V system environment.
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
2D
3 2 1 20 19
4
18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74LVTH373DW
LVTH373
SN74LVTH373DWR
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74LVTH373NSR
SN74LVTH373DBR
LVTH373
LXH373
Tube
TSSOP − PW
Tape and reel
SN74LVTH373PW
LXH373
SN74LVTH373PWR
CDIP − J
Tube
SNJ54LVTH373J
SNJ54LVTH373J
−55°C to 125°C CFP − W
Tube
SNJ54LVTH373W SNJ54LVTH373W
LCCC - FK
Tube
SNJ54LVTH373FK SNJ54LVTH373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




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SN74LVTH373 Datasheet Preview

SN74LVTH373 Datasheet

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES

No Preview Available !

SN54LVTH373, SN74LVTH373
3.3ĆV ABT OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCBS689H − MAY 1997 − REVISED OCTOBER 2003
description/ordering information (continued)
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE 1
LE 11
C1
3
1D
1D
2
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74LVTH373
Description 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
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