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SNJ54HC109J - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

General Description

These devices contain two independent J-K positive-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

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Full PDF Text Transcription for SNJ54HC109J (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SNJ54HC109J. For precise diagrams, and layout, please refer to the original PDF.

D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W PACKAGE SN74HC109 . ...

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Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W PACKAGE SN74HC109 . . . D, N, OR NS PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN54HC109, SN74HC109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 D Low Power Consumption, 40-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V SN54HC109 . . .

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