SNJ54HC109J Datasheet | Texas Instruments

description /ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP - N Tube of 25 SN74HC109N SN74HC109N Tube of 40 SN74HC109D - 40°C to 85°C SOIC - D Reel of 2500 Reel of 250 SN74HC109DR SN74HC109DT HC109 - NS Reel of 2000 SN74HC109NSR HC109 CDIP - J Tube of 25 - 55°C to 125°C CFP - W Tube of 150 SNJ54HC109W SNJ54HC109W LCCC - FK Tube of 55 SNJ54HC109FK SNJ54HC109FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all...