Description
ordering information
These devices contain two independent J-K positive-edge-triggered flip-flops.A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.Clock triggering occurs at a voltage level and is not related directly to the rise time.
