Datasheet Details
| Part number | SNJ54HC109J |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 1.08 MB |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | SNJ54HC109J-etcTI.pdf |
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Overview: D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W PACKAGE SN74HC109 . . . D, N, OR NS PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN54HC109, SN74HC109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 D Low Power Consumption, 40-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V SN54HC109 . . .
| Part number | SNJ54HC109J |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 1.08 MB |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | SNJ54HC109J-etcTI.pdf |
|
|
|
/ordering information These devices contain two independent J-K positive-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
| Part Number | Description |
|---|---|
| SNJ54HC109FK | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| SNJ54HC109W | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| SNJ54HC10FK | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| SNJ54HC10J | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| SNJ54HC10W | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| SNJ54HC112FK | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| SNJ54HC112J | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| SNJ54HC112W | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| SNJ54HC148FK | 8-LINE TO 3-LINE PRIORITY ENCODERS |
| SNJ54HC148J | 8-LINE TO 3-LINE PRIORITY ENCODERS |