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SNJ54HC112W Datasheet Preview

SNJ54HC112W Datasheet

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

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SN54HC112, SN74HC112
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
description/ordering information
The ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
CLK pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops perform as toggle flip-flops by tying J and
K high.
SN54HC112 . . . J OR W PACKAGE
SN74HC112 . . . D OR N PACKAGE
(TOP VIEW)
1CLK 1
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
2Q 7
GND 8
16 VCC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 2Q
SN54HC112 . . . FK PACKAGE
(TOP VIEW)
1J
1PRE
NC
1Q
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLR
2CLK
NC
2K
2J
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC112N
SN74HC112N
−40°C to 85°C
SOIC − D
Tube of 40
Reel of 2500
Reel of 250
SN74HC112D
SN74HC112DR
SN74HC112DT
HC112
CDIP − J
Tube of 25
SNJ54HC112J
SNJ54HC112J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC112W
SNJ54HC112W
LCCC − FK
Tube of 55
SNJ54HC112FK
SNJ54HC112FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




etcTI

SNJ54HC112W Datasheet Preview

SNJ54HC112W Datasheet

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

No Preview Available !

SN54HC112, SN74HC112
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
L
L
Q0 Q0
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
H
X
X
Q0 Q0
This configuration is nonstable; that is, it does not persist
when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
J
C
C
TG
Q
TG
K
C
C
CLK
CLR
C
C
C
TG
TG
C
C
C
Q
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SNJ54HC112W
Description DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
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