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SNJ54HC112W - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

Download the SNJ54HC112W datasheet PDF (SNJ54HC112J included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for dual j-k negative-edge-triggered flip-flops.

Description

The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

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Note: The manufacturer provides a single datasheet file (SNJ54HC112J-etcTI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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SN54HC112, SN74HC112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 40-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max description/ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse.
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