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SNJ54HC112FK - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

This page provides the datasheet information for the SNJ54HC112FK, a member of the SNJ54HC112J DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS family.

Datasheet Summary

Description

The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

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Datasheet preview – SNJ54HC112FK

Datasheet Details

Part number SNJ54HC112FK
Manufacturer Texas Instruments
File Size 1.01 MB
Description DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
Datasheet download datasheet SNJ54HC112FK Datasheet
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Full PDF Text Transcription

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SN54HC112, SN74HC112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 40-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max description/ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse.
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