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TAS5755M Datasheet Preview

TAS5755M Datasheet

Digital Input Audio Amplifier

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TAS5755M

SLOS982C – AUGUST 2017 – REVISED APRIL 2018

TAS5755M 2 × 50W (2 × 19W + 1 × 50W) Digital Input Audio Amplifier With Integrated

Audio Processor and 2.1 Mode Support

1 Features

•1 Reduced Sol

– Single-chip 2.1, 2.0 and Mono Mode Capable

– Single-filter in Mono (PBTL) Mode.

– Pad-up Package and 80 mΩ RDSON Enhances

Thermal Performance

• High Output Power capable:

– 2 × 19 W +1 × 50 W in 2.1 mode

(2 × 4 Ω + 1 × 6 Ω, 24 V)

– 2 × 50 W in 2.0 mode (2 × 6 Ω, 24 V)

– 1 × 100 W in Mono Mode (1 × 2 Ω, 24 V)

– Wide Voltage Range: 8 V to 26.4 V

• Audio Performance Audio:

– THD+N ≤ 0.05% at 1 kHz (RSPK = 8 Ω, POUT

= 1 W, PVDD = 18 V)

– ICN ≤ 50 µVRMS

– Crosstalk ≤ - 67 dB

– SNR ≥ 104 dB

– BD Modulation Available, for Improved Audio

Performance and Efficiency.

• Integrated Audio Processing:

– 2 × 8 + 1 × 2 Biquads

– Two-band + Single-band configurable Dynamic

Range Control (DRC)

– License-Free 3D Effects

– Signal Mixing and DC blocking filter

– Automatic Rate Detection

• Integrated Self-protection

– Thermal Protection

– Over-current Limit Protection

– Under-voltage Protection

2 Applications

• DTV, UHD and Multi-Purpose Monitors

• Sounds Bars, PC Audio

• General Purpose Audio Equipment

3 Description

The TAS5755M is a single-chip flexible digital audio

solution with integrated processing that supports 2.1

(2 speakers + subwoofer), 2.0 or stereo (2 speakers)

and mono (high power speaker) modes.

Its high efficiency, low 80 mΩ RDSON and pad-up

package allows the device to output up to 2 × 50 W

or 1 × 100 W.

TAS5755M leverages 2 full H-bridges which are used

for each channel in stereo mode. In 2.1 mode,

TAS5755M runs 2 independent speaker channels

using 2 half-bridges while using a full-bridge to drive

a subwoofer. Finally, in mono mode, TAS5755M

supports pre-filter parallel bridge tied load (PBTL)

using only one filter stage to reduce total system size

and cost.

TAS5755M has integrated audio processing. It

includes: signal mixing, DC blocking filters, 2 × 8 + 1

× 2 biquads for equalization. Power limiting is

implemented by leveraging a two-band log-style DRC

and a separate single-band DRC for the subwoofer

channel.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TAS5755M

DFD

14 mm × 6.1 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Efficiency vs Total Output Power

100

20 BTL Mode

10 TA=25qC

RL=6:

0 10

30 40 50

Output Power (W)

PVDD = 12V

PVDD = 18 V

PVDD = 24 V

60 70 80

D02043

Output Power vs Supply Voltage

70 THD+N=1%, R L=4:

65 THD+N=10%, R L=4:

60 THD+N=1%, R L=6:

55 THD+N=10%, R L=6:

10 BTL Mode

5 TA=25qC

8 10 12 14 16 18 20 22 24 26

Supply Voltage (V)

DD00130472

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

etcTI

TAS5755M Datasheet Preview

TAS5755M Datasheet

Digital Input Audio Amplifier

No Preview Available !

TAS5755M

SLOS982C – AUGUST 2017 – REVISED APRIL 2018

www.ti.com

Table of Contents

1 Features .................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 4

6 Pin Configuration and Functions ......................... 5

7 Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information .................................................. 8

7.5 PWM Operation at Recommended Operating

Conditions .................................................................. 8

7.6 DC Electrical Characteristics .................................... 8

7.7 AC Electrical Characteristics (BTL, PBTL)................ 9

7.8 Electrical Characteristics - PLL External Filter

Components............................................................... 9

7.9 Electrical Characteristic - I2C Serial Control Port

Operation ................................................................... 9

7.10 Timing Requirements - PLL Input Parameters ..... 10

7.11 Timing Requirements - Serial Audio Ports Slave

Mode ........................................................................ 10

7.12 Timing Requirements - I2C Serial Control Port

Operation ................................................................ 10

7.13 Timing Requirements - Reset (RESET)................ 10

7.14 Typical Characteristics .......................................... 13

8 Parameter Measurement Information ................ 21

9 Detailed Description ............................................ 21

9.1 Overview ................................................................. 21

9.2 Functional Block Diagrams ..................................... 21

9.3 Feature Description................................................. 24

9.4 Device Functional Modes........................................ 34

9.5 Programming........................................................... 36

9.6 Register Maps ......................................................... 41

10 Application and Implementation........................ 59

10.1 Application Information.......................................... 59

10.2 Typical Applications .............................................. 59

11 Power Supply Recommendations ..................... 68

11.1 DVDD and AVDD Supplies ................................... 68

11.2 PVDD Power Supply ............................................. 68

12 Layout................................................................... 68

12.1 Layout Guidelines ................................................. 68

12.2 Layout Examples................................................... 69

13 Device and Documentation Support ................. 71

13.1 Device Support .................................................... 71

13.2 Documentation Support ....................................... 71

13.3 Community Resources.......................................... 71

13.4 Trademarks ........................................................... 71

13.5 Electrostatic Discharge Caution ............................ 71

13.6 Glossary ................................................................ 71

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (January 2018) to Revision C

Page

• Changed "DVSSO" in OSC_RES Pin Description to "DVSS_OSC ground." ........................................................................ 6

• Added RθJA in Thermal Information Table............................................................................................................................... 8

• Changed RθJC(top) in Thermal Information Table ..................................................................................................................... 8

• Added RθJB in Thermal Information Table............................................................................................................................... 8

• Added ΨJT in Thermal Information Table................................................................................................................................ 8

• Added RθJC(bot) in Thermal Information Table ......................................................................................................................... 8

Changes from Revision A (November 2017) to Revision B

Page

• Changed SE Mode, PVDD = 24 V, RL = 4Ω, 7% THD from 17.1 W to 17.6 W in AC Electrical Characteristics (BTL,

PBTL) ..................................................................................................................................................................................... 9

• Changed SE Mode, PVDD = 24 V, RL = 4Ω, 10% THD from 18.1 W to 19 W in AC Electrical Characteristics (BTL,

PBTL) ..................................................................................................................................................................................... 9

• Changed Figure 6 and Figure 7 .......................................................................................................................................... 13

• Changed Figure 19, Figure 20, and Figure 21 ..................................................................................................................... 16

• Changed Figure 33, Figure 34, and Figure 35 .................................................................................................................... 19

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Digital Input Audio Amplifier

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Digital Input Audio Amplifier

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