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TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16× Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data
Set Interrupts Independentl
TL16C550B Datasheet
