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TLC3548 Datasheet Preview

TLC3548 Datasheet

ANALOG-TO-DIGITAL CONVERTERS

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TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
D 14-Bit Resolution
D Maximum Throughput 200 KSPS
D Analog Input Range 0-V to Reference
Voltage
D Multiple Analog Inputs:
– 8 Channels for TLC3548
– 4 Channels for TLC3544
D Pseudodifferential Analog Inputs
D SPI/DSP-Compatible Serial Interfaces With
SCLK up to 25 MHz
D Single 5-V Analog Supply; 3-/5-V Digital
Supply
D Low Power:
– 4 mA (Internal Reference: 1.8 mA) for
Normal Operation
– 20 µA in Autopower-Down
D Built-In 4-V Reference, Conversion Clock
and 8x FIFO
D Hardware-Controlled and Programmable
Sampling Period
D Programmable Autochannel Sweep and
Repeat
D Hardware Default Configuration
D INL: ±1 LSB Max
D DNL: ±1 LSB Max
D SINAD: 80.8 dB
D THD: –95 dB
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
A2
A3
TLC3548
DW OR PW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CSTART
AVDD
AGND
BGAP
REFM
REFP
AGND
AVDD
A7
A6
A5
A4
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
TLC3544
DW OR PW PACKAGE
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
CSTART
AVDD
AGND
BGAP
REFM
REFP
AGND
AVDD
A3
A2
description
The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS
analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V
digital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serial
input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS,
slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The
frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters
connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual
converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such
as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on,
and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS)
are needed to interface with the host.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000 – 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




etcTI

TLC3548 Datasheet Preview

TLC3548 Datasheet

ANALOG-TO-DIGITAL CONVERTERS

No Preview Available !

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
description (continued)
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog
multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART to
extend the sampling period (extended sampling). The normal sampling period can also be programmed as short
sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among
high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power
consumption. The power saving feature is further enhanced with software power-down/ autopower-down
modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter
can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548
have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V
external reference is used.
TA
0°C to 70°C
40°C to 85°C
AVAILABLE OPTIONS
PACKAGED DEVICES
20-TSSOP
(PW)
20-SOIC
(DW)
24-SOIC
(DW)
TLC3544CPW TLC3544CDW TLC3548CDW
TLC3544IPW TLC3544IDW TLC3548IDW
24-TSSOP
(PW)
TLC3548CPW
TLC3548IPW
functional block diagram
DVDD AVDD
REFP
BGAP
REFM
4-V
Reference
X8 X4
A0 A0
A1 A1
A2 A2
A3 A3
A4 X
A5 X
A6 X
A7 X
SDI
SCLK
CS
FS
CSTART
Analog
MUX
OSC
Command
Decode
CMR (4 MSBs)
SAR
ADC
Conversion
Clock
CFR
FIFO
X8
SDO
4-Bit
Counter
Control
Logic
EOC/INT
DGND AGND
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number TLC3548
Description ANALOG-TO-DIGITAL CONVERTERS
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TLC3548 Datasheet PDF






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