* Fully Integrated Signal Conditioning Transceiver
* 1.0
–1.3 Gbps Operation
* Low Power CMOS Design (<300 mW)
* High Differential Output V.
* Resynchronization in Both Directions for 1.25 Gbps Links
* Repeater for 1.0625 Gbps Applications
DESCRIPTION
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TLK1002A is a single-chip dual signal conditioning transceiver.
This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied referenc.
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