TMS320C6211 Datasheet | Texas Instruments

Features - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization D L1/L2 Memory Architecture - 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) - 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) - 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) TMS320C6211, TMS320C6211B FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SPRS073L - AUGUST 1998 - REVISED JUNE 2005 D Device Configuration - Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot - Endianness: Little Endian, Big Endian D 32-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories: SRAM and EPROM - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - 512M-Byte Total Addressable External Memory Space D Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) D 16-Bit Host-Port Interface (HPI) - Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (Mc BSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching patible - Up to 256 Channels Each - AC97-patible - Serial-Peripheral-Interface (SPI) patible (Motorola) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked-Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan-patible D 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN...