TMS320C6201 Datasheet | Texas Instruments

Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel D 16-Bit Host-Port Interface (HPI) -- Access to Entire Memory Map TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 GJC/GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 D Two Multichannel Buffered Serial Ports (Mc BSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching patible -- Up to 256 Channels Each -- AC97-patible -- Serial Peripheral Interface (SPI) patible (Motorola™) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan patible D 352-Pin BGA Package (GJC Suffix) D 352-Pin BGA Package (GJL Suffix) D CMOS Technology -- 0.18-μm/5-Level Metal Process D 3.3-V I/Os, 1.8-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Veloci TI and TMS320C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. PRODUCTION DATA information is...