TMS320C6205 Datasheet | Texas Instruments

Features - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization D 1M-Bit On-Chip SRAM - 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) - 512K-Bit Dual-Access Internal Data (64K Bytes) - Organized as Two 32K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) - Glueless Interface to Synchronous Memories: SDRAM or SBSRAM - Glueless Interface to Asynchronous Memories: SRAM and EPROM - 52M-Byte Addressable External Memory Space D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D Flexible Phase-Locked-Loop (PLL) Clock Generator TMS320C6205 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS106G - OCTOBER 1999 - REVISED JULY 2006 D 32-Bit/33-MHz Peripheral ponent Interconnect (PCI) Master/Slave Interface Conforms to: PCI Specification 2.2 Power Management Interface 1.1 Meets Requirements of PC99 - PCI Access to All On-Chip RAM, Peripherals, and External Memory (via EMIF) - Four 8-Deep x 32-Wide FIFOs for Efficient PCI Bus Data Transfer - 3.3/5-V PCI Operation - Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O - Supports 4-Wire Serial EEPROM Interface - PCI Interrupt Request Under DSP Program Control - DSP Interrupt Via PCI I/O Cycle D Two Multichannel Buffered Serial Ports (Mc BSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching patible - Up to 256 Channels...